The invention relates generally to semiconductor devices, and more particularly to a transistor having a shaped gate electrode structure.
In many prior art semiconductor transistors a generally uniform vertical gate profile was often desired. This is due to the fact that a generally uniform vertical gate would reduce parasitic electric effects associated with non-vertical gate profiles. Conventional etching techniques result in slight lateral etching at the top of the gate because the masking layer is gradually eroded during the etch. This results in a slight taper of the gate (narrow at the top, wide at the bottom near dielectric). This is undesirable, since the top is typically silicided, and narrowing here limits electrical conduction. Also, due to concerns with over etching of the underlying gate dielectric or substrate, etching processes had to be closely controlled to minimize such potentially damaging over etching conditions. As such, tapered regions or xe2x80x9cfeetxe2x80x9d that extend horizontally from the generally vertical gate profile could result at the interface of the gate and the underlying gate oxide. These tapered regions are undesirable due to the additional parasitics that they introduce, where one such additional parasitic is an increase in the Miller capacitance of the transistor.
Although generally vertical gate profiles do reduce some parasitics, such profiles limit the potential for optimization of the device architecture in which they are included. Such optimizations can be based on different implantation steps, where some of these implementation steps may utilize angular implantation. Due to the generally vertical profile of the gate structure, closely spaced devices can limit the angle with which such angular implantation steps can be performed. In many cases, the offset between different implantation steps is important, and the limitation of the maximum angle with which specific angular implantation steps can be performed restricts the maximum offset that can be achieved between different implantation steps. This problem is compounded as device densities on integrated circuits continue to increase.
Therefore, gate structures that allow for more selective and controllable etching operations as well as increased effective angles of implantation are desired.